The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for loading a phase-locked loop (PLL) configuration using Flash memory.
A phase-locked loop (PLL) is a control system that generates an output signal whose phase is related to the phase of an input signal. While there are several differing types of PLLs, a PLL may be visualized as an electronic circuit consisting of a variable frequency oscillator and a phase detector. The variable frequency oscillator generates a periodic signal, and the phase detector compares the phase of that signal with the phase of the input periodic signal, adjusting the variable frequency oscillator to keep the phases matched. Bringing the output signal back toward the input signal for comparison is called a feedback loop since the output is “fed back” toward the input forming a loop.
Phase-locked loop (PLL) modules are used to set internal clock frequencies at which a device, for example a core synchronous logic of an Application Specific Integrated Circuit (ASIC), operates. These PLL modules have many inputs (over 100 typically) that configure the PLL to produce one or more clock signals of certain frequencies. A default setting for these inputs will be determined during a design phase of the device in which the PLL operates. The PLL module will have a reset, which will be driven by the device's logic during initialization, at which point the PLL will apply a set of default settings upon the reset to lock at the desired frequency. The default settings will be designed into the device internal ground/positive power supply (GND/VDD) ties to the PLL module inputs.